This invention relates to the field of power conditioning systems. More specifically, to power conditioning systems incorporating DC-DC conversion systems preceded by a power factor correction stage. Even more specifically, to power conditioning systems in which a control signal is generated to enable functioning of DC-DC power conversion systems during the periods in which power is initially supplied to and removed from the DC-DC power conversion systems.
Power factor correction (PFC) is well known to reduce AC line input current harmonic distortion in power conversion systems. In a power conversion system utilizing a PFC stage, it is critical that the PFC stage be fully functional before any downstream DC-DC power conversion circuitry is allowed to function. Previous designs accomplish this power-up, or sequencing delay, through the use of capacitor-based timing circuitry which is designed to inhibit DC-DC converter turn-on for a time sufficient for the PFC stage to attain its operational output voltage. The use of such timing circuitry, however, necessitates relatively long idle periods between start-up sequences to ensure correct timing. If the power supply to a capacitor-based start-up delay circuit is rapidly switched on and off, such as may occur in hot swap conditions, the timing capacitor voltage at each power application can vary, resulting in incorrect time delays.
A second consideration in many applications of a DC-DC power conversion system is the desirability, following loss of input power, of maintaining the system output voltage above some specified minimum voltage for a given period, usually referred to as the xe2x80x9chold-up timexe2x80x9d. This hold-up provision enables the DC-DC conversion device to continue supplying power to the load through brief AC input line voltage dips and to provide capability for the equipment load to power-down in a controlled manner during an actual loss of power.
In many DC-DC converter designs, this hold-up time is determined by sizing the output capacitors for energy storage sufficient to support the load voltage for the required duration. The resulting capacitance usually ends up being far in excess of that required for output ripple voltage smoothing. In a low-power system design this practice probably has little economic impact, but in a high-power design the added cost can be significant.
Moreover, the added capacitance is not employed efficiently; if the allowable voltage drop during hold-up is 10 percent (typical), only 19 percent of the stored capacitor energy is useful for hold-up.
Some prior designs for hold-up rely on auxiliary storage capacitors which can be switched to various locations in the circuit design. See Bosse, et al., U.S. Pat. No. 4,743,835. Bosses et al. is incorporated herein by this reference. For the present invention, however, such auxiliary capacitors and switching means are extraneous. Consider, for example, the operation of the power conversion system design which incorporates a PFC stage having an output capacitor followed by one (or more) DC-DC conversion devices. In most PFC stage designs, the output capacitor operating voltage is about 10 to 20 percent above the peak AC line voltage; for a high-power system, line input will usually be nominally 220VAC rms with a high input line peak voltage of 370VAC and an output capacitor operating voltage of 400VDC. With loss of line input, the PFC stage ceases supplying power, but the DC-DC conversion device continues operating from the stored energy of the capacitor at its input. For DC-DC conversion devices designed to operate at 400VDC input (i.e. from the PFC stage output), it is usually not difficult or particularly costly to design for operation with input voltage at 70 to 50 percent of maximum during a brief hold-up period. This in turn means that about 50 to 75 percent of the PFC stage output capacitor stored energy can be utilized to power the DC-DC conversion device during the hold-up period. Under the conditions just set forth, the minimum output capacitance inherent in a PFC stage design would provide hold-up power for 25 to 40 milliseconds with the DC-DC conversion device maintaining output regulation; an increase in capacitance above the inherent minimum would correspondingly increase this time. When the DC-DC conversion device ceases functioning, its output capacitance will provide some additional hold-up time, the exact duration depending on both the value of capacitance and the amount of voltage sag which the equipment load will tolerate.
Under a loss of power scenario, the DC-DC power conversion device will experience a steadily decreasing input voltage as energy from the PFC stage output capacitor is used for hold-up. At some point, this input voltage will drop below that value required for proper functioning of the DC-DC power conversion device. It is important that the DC-DC conversion device be shut down properly while the input voltage is still adequate for proper operation; in high-power conversion systems, allowing operation to cease from collapsing input voltages, rather than shutting down, risks anomalous operating conditions with potential damage to power circuitry.
It is apparent, then, that during power-up a voltage threshold circuit is needed that can power the DC-DC converter at the proper PFC stage output voltage and functions independent of rapid power supply switching conditions such as during a hot swap.
Additionally, during loss of line power, a similar threshold circuit is needed that disables the DC-DC conversion device when it determines the capacitor voltage has dropped to or below a predetermined level. Previous power-up or hold-up sequencing circuitry designs have not combined power-up and hold-up control functionality due to these differing voltage threshold requirements. The present invention encompasses accurate alterable voltage threshold circuitry which provides full functionality for both power-up and hold-up sequences utilizing different voltage thresholds.
It is therefore an object of this invention to provide an improved power-up sequencing that provides accurate threshold functionality during rapid power switching conditions such as may occur during a hot swap.
It is a further object of this invention to provide an improved hold-up control system that provides accurate threshold functionality following loss of input power.
It is a still further object of this invention to provide a combined power-up sequencing and hold-up control system that provides full functionality for both power-up sequence and hold-up control that utilize different voltage thresholds.
This invention results from the realizations that a) the imprecision and complexity of capacitor-based timing circuits cause them to be unsuitable for proper power-up sequencing of a PFC stage/DC-DC conversion device power system; b) a far more reliable approach for power-up sequencing is to determine when the PFC stage output voltage has reached a proper operating threshold and to enable the DC-DC conversion device upon detecting attainment of that threshold; c) a design for hold-up time based solely on discharge of energy from the DC-DC conversion device output capacitors can lead to unduly high values for such output capacitors; d) the PFC stage output capacitor is better suited and more efficient for supplying energy for hold-up upon loss of system input power; e) the proper control of the DC-DC conversion device requires shutdown of that device when its input voltage has decreased to some predetermined design value; and f) all such objections, constraints and criteria are well met using a comparator circuit accurately to detect voltage levels and to provide for change of the threshold voltage from a first threshold for power-up sequencing to a second threshold for hold-up control.
This invention features a voltage threshold circuit with a comparator for (i) comparing a predetermined threshold voltage to the output voltage of a power factor correction stage of a power conditioner and (ii) outputting a signal if the output voltage is at least equal to the predetermined threshold voltage. The presence of the signal decreases the predetermined threshold voltage, thereby creating a hysteresis effect in the switching on and off of the comparator signal.